This invention relates to detector circuitry, and in particular, to low power high sensitivity MOS detector circuits.
Many of today's large capacity MOS dynamic memories require input buffers and sense-refresh detectors which have relatively low power dissipation and relatively high sensitivity. Typically, these memories use a basic memory cell which consists of an MOS transistor with a capacitor coupled to one of the output terminals. The ever increasing demand for greater and greater memory storage on a single chip has caused designers to decrease the size of the memory cell and thereby decrease the output signal therefrom. The reduction in the magnitude of the output signal level increases the need for higher sensitivity sense-refresh detectors. As the number of memory cells on a single integrated circuit chip increases, the number of sense-refresh detectors increases and power dissipation becomes increasingly important.
It would be desirable to have a basic detector which has relatively high sensitivity and low power dissipation, and which is capable of being fabricated on the same integrated circuit chip which contains the MOS memory cells.